The present invention is directed to memory controllers and in particular to controllers for multiplexed-address memories.
Two of the most remarkable aspects of computer development in recent times have been microprocessor-speed increases and computer users' seemingly unlimited appetite for memory capacity. Because of reductions in integrated-circuit-chip feature sizes and improvements in architecture, microprocessor speed has increased rapidly, and much of the increased memory-capacity demand has resulted from the complexity of the human-to-computer interface problem.
Like microprocessors, memory circuits have enjoyed some speed increase. Memory-speed increases have not been nearly as great as microprocessor-speed increases, however, and memory access time has accordingly been the limiting factor in many computer applications.
Among the factors that slow the operation of integrated circuits generally and memory circuits in particular are propagation delays resulting from signal-path lengths. Significant speed reductions accordingly result from decreasing memory-chip size. Moreover, the sizes of many products are influenced significantly by their memory sizes. The memory type of choice for most large semiconductor memories is accordingly the dynamic random-access memory (DRAM), which employs charge storage to retain information. It thus requires fewer transistors--and thus less space--for a given memory capacity than static RAMs do.
The most popular type of DRAM is the multiplexed-address version, which employs address multiplexing to limit chip size further. In operation, a transition in a row-address-strobe (RAS) signal strobes half of the address bits (the "row address=38 ) from the DRAM's address terminals into address registers in the DRAM. The remaining address bits (the "column address") are then applied to the address terminals, and a transition in a column-address-strobe (CAS) signal causes the requested access to occur at the address specified by the concatenation of the internal-register contents and the signals that are on the address lines at the time of the CAS transition. By employing multiplexing, such a chip requires only half as many address terminals as it otherwise would, and it thereby saves space.
Of course, the need to apply the address signals in two steps compromises to some extent the speed advantage that the size reduction affords. Since overall computer operation is so dependent on memory access time, therefore, memory manufacturers have developed "page-mode" addressing to circumvent this problem to some extent. In accordance with this technique, the chip is so made that it does not require a separate RAS transition for every memory access. Specifically, if the row address for a given access is the same as that for the previous access, that access can be caused by simply applying a second CAS transition with the new column address, i.e., without applying a second RAS transition. All that is required is that the RAS signal be held at the (asserted) level that it assumed as a result of the strobing transition in the previous access. This causes the DRAM to retain the row address for use in the next access.
Computer makers and others have accordingly exploited this feature by employing a type of memory controller that responds to a sequence of memory-access requests by keeping the RAS line asserted until it receives a refresh request or a request for access to a location on a different "page," i.e., to a location having a different row address. When the memory controller receives a different row address, it deasserts the RAS line for a period of time necessary for the chip's sense amplifiers and bit lines to "precharge," as they must in all DRAMs before a row-address change. The row address is then applied to the chip and strobed in with a new RAS assertion, and operation proceeds in the normal manner.
Some memory-controller designers have extended this approach. For instance, some memory controllers keep the RAS line asserted, even when no memory access is pending, until a new access is requested or (in the cases of a dynamic memory) a refresh operation must be performed. Indeed, some designers have gone to the extent of causing the controller to re-apply the previous row address to the chip after a refresh operation.
Actually, this expedient of keeping the RAS line asserted during idle times can exact a penalty when a row-address change occurs. If the RAS line were not held, any idle time between memory accesses could be used for precharging, and this would reduce or eliminate the pre-charge delay involved in the next memory access. Since the majority of memory accesses in most applications are directed to the same pages as the accesses that immediately precede them, however, the speed benefits that result from page "hits" greatly outweigh the speed penalties that result from page "misses."